Method for forming extension by using double etch spacer

ABSTRACT

A method for forming extension by using double etch spacer. The method at least includes the following steps. First of all, provide a semiconductor substrate. Then, forms the gate on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted to substrate by a mask of both the gate and the first spacer to form the source/drain region. Then, form the second spacer by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted to substrate by a mask of both the gate and the second spacer to form an extension.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a method for manufacturing a metal-oxide-semiconductors transistor, and more particularly to a method that control the extension lateral diffusion by using double etch spacer.

[0003] 2. Description of the Prior Art

[0004] In the field of metal oxide semiconductors, the length of channel will become shorter as the size of device be decreased, and the operation time will become shorter too. However, the length of channel of MOSFET can't be shorten unlimitedly, the short channel of device will result in some problems, they are so called short channel effect.

[0005] Hot carrier effect will be more serious as shorten the channel of MOSFET further. There are many methods to solve the issue, and one of them is to lower the operation voltage of MOSFET. If, for example, lower the voltage from 5V to 2.5V, it will let the electric field too weak to result in hot carrier, and hot carrier effect will be lessened effectly. Other method to lessen the hot carrier effect at least includes lightly doped drain (LDD), and is called as extension while the concentration is increased. In such way, add a low concentration N-type region into portion region of source/drain region of MOSFET, and the region is near the channel of device.

[0006] In conventional process, provide a substrate with the gate oxide layer in the metal oxide semiconductors, and form a gate on it, and form an extension by implanting numerous first ions in the substrate, and then form the spacer on the sidewalls of the gate. Then, form the source/drain region by implanting numerous second ions in the substrate. Because form a gate, first form an extension and then form the source/drain region, wherein extension can effective to avoid many times thermal process and initial lateral diffuse, such as deposition reaction and ions implantation. If the width of the effective channel length is too short, the short channel effect more severe.

[0007] For the foregoing reasons, there is a need for a method of forming extension by using double etch spacer to solve short channel effect.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, a method is provided for forming extension by using double etch spacer of MOS and substantially can be used to solve lateral diffuse issue in conventional process.

[0009] One of the objectives of the present invention that let extension accept less and less thermal process.

[0010] Another of the objective of the present invention that control the strength of short channel effect for suppressing short channel effect in deep submicron.

[0011] A further objective of the present invention that control the strength of spacer for collocating lateral diffuse by using double etch spacer.

[0012] In order to achieve the above objects of this invention, the present invention provides a method for forming extension by using double etch spacer. The method at least includes the following steps. First of all, provide a semiconductor substrate. Then, forms the gate on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted to substrate by a mask of both the gate and the first spacer to form a source/drain region. Then, form the second spacer by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted to substrate by a mask of both the gate and the second spacer to form an extension.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by referring to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0014]FIG. 1A is cross-sectional view of a structure having the gate, the spacer and the source/drain region sequentially form thereon in accordance with one embodiment of the present invention;

[0015]FIG. 1B is cross-sectional view of forming the silicide over the structure FIG. 1A;

[0016]FIG. 1C is cross-sectional view of etching the spacer over the structure of FIG. 1 B; and

[0017]FIG. 1D is cross-sectional view of forming an extension by implanting numerous ions closed to the structure of FIG. 1C.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018] Some embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.

[0019]FIG. 1A to FIG. 1D are cross-sectional views of a method for forming extension of using double etch spacer process in accordance with one embodiment of the present invention.

[0020] Referring to FIG. 1A, first provide a semiconductor substrate 100 which comprises polysilicon substrate, and forms the gate oxide layer 102 on the semiconductor substrate 100. Then, forms the gate 104 on the gate oxide layer 102, and forms the first spacer 106 on a sidewall of the gate 104. Then, numerous first ions are implanted to substrate 100 by a mask of both the gate 104 and the first spacer 106 to form the source/drain region 108, whereby, available varieties of first ions at least include B⁺³ and BF₂ ⁺.

[0021] Referring to FIG. 1B, an optional step is that a silicide 110 is formed on the gate 104 and on the substrate 100. Silicide 110 comprises TiSi₂ and CoSi₂, and silicide 110 usually is formed by the rapid thermal process.

[0022] Referring to FIG. 1C, as a key step in this invention, form the second spacer 112 by etching first spacer 106, wherein the width of the second spacer is less than the width of the first spacer 106, and second spacer 112 is formed by anisotropic etch method.

[0023] Finally, referring to FIG. 1D, numerous second ions are implanted to substrate 100 by a mask of both the gate 104 and the second spacer 112, whereby, available varieties of second ions at least include B⁺³ and BF₂ ⁺. Next, a low concentration region, extension 114 is formed in portion region of source/drain regions 108. Obviously, because that extension 114 is formed after source/drain regions has been formed, lateral diffusion of extension 114 can be effectively provided by avoiding thermal processes such as deposition reaction and ions implantation. In other ways, for the present invention, contuse of extension 114 is not obviously broaden for only a thermal process is used after second ions are implanted. Thus, effective length of channel is properly controlled and then effect of the short channel effect is properly decreased.

[0024] In accordance with the present invention, it is apparent that there has been provided a method of forming extension by using double etching spacer which overcomes the disadvantages of the prior art. The present invention is inexpensive and uncomplicated, can easily be integrated into conventional process flows without significantly increasing cycle time and to decrease thermal process.

[0025] Although specific embodiment have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims. 

What is claimed is:
 1. A method for forming a transistor, comprising: providing a semiconductor substrate; forming a gate on said substrate; forming a first spacer on a sidewall of said gate; using said gate and said first spacer as a mask to form a source/drain region by implanting a plurality of first ions in said substrate; forming a second spacer by etching said first spacer, wherein the width of said second spacer is less than the width of said first spacer; and using said gate and said second spacer as a mask to form an extension by implanting a plurality of second ions in said substrate.
 2. The method according to claim 1, wherein said semiconductor substrate comprises silicon substrate.
 3. The method according to claim 1, wherein said first spacer is formed by an anisotropic etch.
 4. The method according to claim 1, wherein said first ions and said second ions have the same electricity.
 5. The method according to claim 1, wherein available varieties of said first ions comprise B⁺³ and BF₂ ⁺.
 6. The method according to claim 1, wherein available varieties of said second ions comprise B⁺³ and BF₂ ⁺.
 7. The method according to claim 1, further comprises to change the contour of said extension by performing a rapid thermal process after said second ions are implanted.
 8. A method for forming a transistor, comprising: providing a semiconductor substrate; forming a gate on said substrate; forming a spacer on a sidewall of said gate; using said gate and said first spacer as a mask to form a source/drain region by implanting a plurality of first ions in said substrate; forming a silicide on top of said gate and the surface of said source/drain region; forming a second spacer by etching said first spacer, wherein the width of said first spacer is less than the width of said first spacer; and using said gate and said second spacer as a mask to form an extension by implanting a plurality of second ions in said substrate.
 9. The method according to claim 8, wherein said semiconductor substrate comprises silicon substrate.
 10. The method according to claim 8, wherein said first spacer is formed by an anisotropic etch.
 11. The method according to claim 8, wherein said first ions and said second ions have the same electricity.
 12. The method according to claim 8, wherein available varieties of said first ions comprise B⁺³ and BF₂ ⁺.
 13. The method according to claim 8, wherein available varieties said second ions comprise B⁺³ and BF₂ ⁺.
 14. The method according to claim 8, wherein available varieties of said silicide comprises TiSi₂ and CoSi₂.
 15. The method according to claim 8, further comprises to change the contour of said extension by performing a rapid thermal process after said second ions are implanted. 